A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies

Recent advances in FPGA (Field-Programmable Gate Array) technologies have made feasible the implementation of low-cost parallel computing platforms for highperformance matrix computations. Compared to conventional multiprocessor systems, the resulting MultiProcessors-On-a-Programmable-Chip (MPoPCs) can provide unique advantages and opportunities in both software and hardware. It is shown in this paper that the performance of an MPoPC can be improved dramatically by adapting slightly IP(Intellectual Property)-based processing elements, and customizing the memory and the interconnection network. The parallel LU factorization of large, sparse Doubly-Bordered Block Diagonal (DBBD) matrices is employed as an application example. To enhance further the performance by software techniques, a run-time load balancing strategy for this algorithm is proposed and analyzed. Extensive experimental results on benchmark matrices of size up to 7917 x 7917 for power networks demonstrate the effectiveness of our effort.